1. Technical Field
The present invention relates to semiconductor memory devices having self-correcting functions and more particularly to a semiconductor memory device having a self-correcting function for correcting errors without using an error-correcting circuit in an EEPROM which employs a MOS floating-gate having a tunnel oxide film on the drain as a memory cell.
2. Prior Art
The probability that faulty bits occur increases in the case of a ROM having a capacity of over 1M bits and this results in decreasing product yield. For this reason, redundant memory cells have heretofore been provided to improve the product yield and simultaneously to remedy faulty memory cells or the whole faulty memory. A memory cell for storing a parity bit, a parity check circuit, a built-in ECC circuit and the like are otherwise provided to detect errors in bits, so that faulty bits are partially remedied.
However, the use of such redundant memory cells makes it troublesome to remedy the faulty bits by means of internal wiring. The drawback in this case is that chip dimensions are likely to become doubled in the system of making a spare memory cell 100% redundant.
In the remedial method using the ECC circuitry, on the other hand, a memory cell for storing parity data is required and if the cell is made to have an error-correcting function in particular, it is insufficient to add a 1-bit parity bit to each data. With 4-bit parity relative to 8-bit data, for instance, the whole cell volume will increase by 1.5 times greater, compared with normal data storage. However, this arrangement is disadvantageous in that the chip area also tends to increase.